Survey of Soft Error Mitigation Techniques Applied to LEON3 Soft Processors on SRAM-Based FPGAs

Soft-core processors implemented in SRAM-based FPGAs are an attractive option for applications to be employed in radiation environments due to their flexibility, relatively-low application development costs, and reconfigurability features enabling them to adapt to the evolving mission needs. Despite the advantages soft-core processors possess, they are seldom used in critical applications because they are more sensitive to radiation than their hard-core counterparts. For instance, both the logic and signal routing circuitry of a soft-core processor as well as its user memory are susceptible to radiation-induced faults. Therefore, soft-core processors must be appropriately hardened against ionizing-radiation to become a feasible design choice for harsh environments and thus to reap all their benefits. This survey henceforth discusses various techniques to protect the configuration and user memories of an LEON3 soft processor, which is one of the most widely used soft-core processors in radiation environments, as reported in the state-of-the-art literature, with the objective of facilitating the choice of right fault-mitigation solution for any given soft-core processor

Survey of Lockstep based Mitigation Techniques for Soft Errors in Embedded Systems

Soft errors are one of the significant design technology challenges at smaller technology nodes and especially in radiation enviro nments. This paper presents a particular class of approaches to provide reliability against radiation-induced soft errors. The paper provides a review of the lockstep mechanism across different levels of design abstraction: processor design, architectural level, and the software level. This work explores techniques providing modifications in the processor pipeline, techniques allied with FPGA dynamic reconfiguration strategies and different types of spatial redundancy

Using Machine Learning for Anomaly Detection on a System-on-Chip under Gamma Radiation

The emergence of new nanoscale technologies has imposed significant challenges to designing reliable electronic systems in radiation environments. A few types of radiation like Total Ionizing Dose (TID) effects often cause permanent damages on such nanoscale electronic devices, and current state-of-the-art technologies to tackle TID make use of expensive radiation-hardened devices. This paper focuses on a novel and different approach: using machine learning algorithms on consumer electronic level Field Programmable Gate Arrays (FPGAs) to tackle TID effects and monitor them to replace before they stop working. This condition has a research challenge to anticipate when the board results in a total failure due to TID effects. We observed internal measurements of the FPGA boards under gamma radiation and used three different anomaly detection machine learning (ML) algorithms to detect anomalies in the sensor measurements in a gamma-radiated environment. The statistical results show a highly significant relationship between the gamma radiation exposure levels and the board measurements. Moreover, our anomaly detection results have shown that a One-Class Support Vector Machine with Radial Basis Function Kernel has an average Recall score of 0.95. Also, all anomalies can be detected before the boards stop working

Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores

Current multicore platforms contain different types of cores, organized in clusters (e.g., ARM's big.LITTLE). These platforms deal with concurrently executing applications, having varying workload profiles and performance requirements. Runtime management is imperative for adapting to such performance requirements and workload variabilities and to increase energy and temperature efficiency. Temperature has also become a critical parameter since it affects reliability, power consumption, and performance and, hence, must be managed. This paper proposes an accurate temperature prediction scheme coupled with a runtime energy management approach to proactively avoid exceeding temperature thresholds while maintaining performance targets. Experiments show up to 20% energy savings while maintaining high-temperature averages and peaks below the threshold. Compared with state-of-the-art temperature predictors, this paper predicts 35% faster and reduces the mean absolute error from 3.25 to 1.15 °C for the evaluated applications' scenarios

Dataset for Application Control and Monitoring in Heterogeneous Multiprocessor Systems

Dataset supports: Leech, C. et al (2018) Application Control and Monitoring in Heterogeneous Multiprocessor Systems. 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</span

Memory and thread synchronization contention-aware DVFS for HPC systems

Due to the operating costs and failure rates of computing platforms, energy efficiency has become a major concern for modern and future many-core systems. In the quest for high performance, the power consumption growth rate must slow down while delivering more performance per unit of power. To improve the energy efficiency of such systems, processors are equipped with low-power techniques such as dynamic voltage and frequency scaling (DVFS) and power capping. These techniques must be controlled carefully as per the workload; otherwise, it may result in significant performance loss and/or power consumption due to system overheads (e.g. DVFS transition latency). Existing approaches [1], [2] are not effective in adapting to workload variations as they do not consider the combined effect of application compute-/memory-intensity, thread synchronization contention, and non-uniform memory accesses (NUMAs) owing to the underlying processor architecture. This poster discusses a workload-aware runtime energy management technique that takes the aforementioned factors into account for efficient V-f control

Dataset for Reliable Mapping and Partitioning of Performance-constrained OpenCL Applications on CPU-GPU MPSoCs

Dataset to support an invited paper for publication in 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia. Weber Wachter, E., Merrett, G. V., Singh, A., &amp; Al-Hashimi, B. (2017). Reliable mapping and partitioning of performance-constrained OpenCL Applications on CPU-GPU MPSoCs. Paper presented at 15th IEEE/ACM Symposium on Embedded Systems for Real-Time Multimedia, Seoul, Korea, Republic of.</span

Workload-Aware runtime energy management for HPC Systems

Energy efficiency has become a crucial factor in high-performance computing, mainly due to its effect on operating costs and failure rates of computing platforms. To improve the energy efficiency of such systems, processors are equipped with low-power techniques such as dynamic voltage and frequency scaling (DVFS) and power capping. These techniques have to be controlled carefully as per the workload; otherwise, it may result in significant performance loss and/or power consumption due to system overheads (e.g. DVFS transition latency). Existing approaches are not effective in adapting to workload variations as they do not consider the combined effect of application compute-/memory-intensity, thread synchronization contention, and nonuniform memory accesses (NUMAs) owing to the underlying processor architecture. In this work, we propose a workload-aware runtime energy management technique that takes the aforementioned factors into account for efficient V-f control. The proposed technique measures the processor workload using Memory Accesses Per Micro-operation (MAPM), and also considers the thread synchronization contention and latency due to NUMAs to select an appropriate V-f setting. This approach also uses workload prediction for pro-Active V-f control to improve the energy consumption and performance loss. The proposed technique has been implemented on the 12-core (24 threads) Intel Xeon E5-2630 and 61-core (244 threads) Xeon Phi many-core platforms, supporting per-core and system-wide DVFS, respectively. When evaluated with different application scenarios, results show an improvement in energy efficiency of up to 81.2% compared to existing approaches.</p

Dataset for &quot;Workload-Aware Runtime Energy Management for HPC Systems&quot;

This dataset supports the article entitled &quot;Workload-Aware Runtime Energy Management for HPC Systems&quot; accepted for publication in International Workshop on Optimization of Energy Efficient HPC &amp; Distributed Systems (OPTIM), July 16&ndash;20, 2018, Orl&eacute;ans, France. </span

Dataset for An Application- and Platform-agnostic Control and Monitoring Framework for Multicore Systems

Dataset supports: Bragg, G. M. et al (2018) An Application- and Platform-agnostic Control and Monitoring Framework for Multicore Systems. 3rd International Conference on Pervasive and Embedded Computing (PEC).</span